The present invention relates to the fabrication of semiconductor integrated circuits (IC's). More particularly, the present invention relates to techniques for reducing mask erosion during the etching of features in a substrate layer.
During the manufacture of a semiconductor-based product, for example, a flat panel display or an integrated circuit, multiple deposition and/or etching steps may be employed. During the deposition step, materials are deposited onto a substrate surface (such as the surface of a glass panel or a wafer). Conversely, etching may be employed to remove materials from predefined areas on the substrate surface.
During etching, a mask formed of a suitable mask material, such as photoresist, is typically employed to define the areas to be etched in the underlying layer. In an exemplary photoresist technique, the photoresist material is first deposited on the underlying layer to be etched. The photoresist material is then patterned by exposing the photoresist material in a suitable lithography system, and by developing the photoresist material to form a mask to facilitate subsequent etching. Using an appropriate etchant, areas of the underlying layer that are unprotected by the mask may then be etched away using an appropriate etchant source gas, thereby forming features such as trenches or vias in the underlying layer.
To facilitate discussion, FIG. 1 depicts an exemplary substrate stack 100, including mask 102, underlying layer 104, and substrate 106. As mentioned, mask 102 may represent photoresist mask or it may be formed of any suitable mask material, including hard mask materials. Underlying layer 104 represents the layer or layers to be etched. For ease of discussion, the underlying layer represents herein a dielectric layer (e.g., a doped or undoped silicon dioxide-containing layer) although, depending on the specific application, the underlying layer may be formed of any etchable material, including for example polysilicon, metal, or the like. Substrate 106 includes the layers and features that underlie the layer to be etched and may include the semiconductor wafer or the glass panel itself. For the purposes of the invention herein, the composition of substrate 106 is somewhat irrelevant.
Within mask 102, there is shown an opening 108, which is created during the mask patterning process. Through opening 108, etchants (or plasma formed from such etchants) react with the material of underlying layer 104 to etch features (e.g., vias or trenches) in the underlying layer.
In any given etch, the challenge has been to formulate an etch process that can achieve a high etch rate through the underlying layer while preserving the desired vertical etch profile and without causing undue damage to the protective mask. The latter consideration is particularly important because if the mask is inadvertently damaged during etching, the areas of the underlying layer that are disposed below the protective mask material may be undesirably etched away, leading to defects in the resultant semiconductor-based product.
To facilitate discussion of the mask erosion issue, FIG. 2 shows the etch result after substrate stack 100 is etched using a conventional plasma-enhanced etching process. As shown in FIG. 2, mask erosion causes some of mask 102 to be removed, as depicted by thickness 202. In the vicinity of opening 108 in mask 102, the mask material is eroded in both the vertical direction (which causes bulk loss 202) and in the horizontal direction to form facet 206. Although not shown in FIG. 2, excessive mask erosion may create a facet large enough to expose the underlying material of layer 104 to the etchant, leading to undesirable damage to underlying layer 104 in the vicinity of opening 108 .
Mask erosion is an even greater challenge in the fabrication of modern high density integrated circuits. To achieve greater circuit density, modern integrated circuits are scaled with increasingly narrower design rules. As a result, the minimum separation between adjacent devices on the integrated circuit has steadily decreased. By way of example, it is not uncommon to employ design rules as small as 0.18 microns or even smaller in the fabrication of some high density integrated circuits. As adjacent devices are packed more closely together, there is a limit on the maximum allowable thickness of the mask layer. This is because if the mask is unduly thick for a given design rule, it may not be possible to properly pattern the mask for etching, for example. As the mask layer becomes thinner and thinner to accommodate the narrow design rules of high density integrated circuits, mask selectivity becomes more and more important to prevent inadvertent mask erosion. Accordingly, there is a need for an etch process that can maximize the overall etch rate and mask selectivity while maintaining the desired substantially vertical etch profile.